ARM Accredited Engineer
Last Update Nov 30, 2025
Total Questions : 210
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On an ARM processor that does not implement Security Extensions, which one of the following can be the starting address of the exception vector table?
A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?
According to the AAPCS (with soft floating point linkage), when the caller "func" calls sprintf, where is the value of the parameter "x" placed?
#include
void func(double x, int i , char *buffer)
{
sprintf(buffer, "pass %d: value = %f\n", i, x); }
When applied to locations in memory configured using a write-back cache strategy, what does a data cache 'clean' operation do?
If a Generic Interrupt Controller (GIC) implements 64 priority levels, which priority field bits hold the priority value?
A program running on a development board that is connected to a host using a debugger can access a file on the host by using:
Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:
What view in a debugger displays the order in which functions were called?
In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?
What will be the contents of R2 after the execution of the following piece of code?
LDRR1, =0xAABBCCDD
MOV R2, #0x4
ANDSR1, R1, #0x4
ADDNE R2, R2, #0x4
Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?
Which of these C99 keywords can be used to indicate that two arrays do not overlap?
The automatic removal of a cache line from a cache to free the location is known as cache line:
Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?
Which TWO of the following options can the ARM Compiler (armcc) directive__packed be used for? (Choose two)
In an experiment, the time taken for an application to complete a given task is measured using a stopwatch. Which THREE of the following make up the total time? (Choose three)
How many bytes of stack are needed to pass parameters when calling the following function?
int foo( short arg_a, long long arg_b, char arg_c, int arg_d )
Which privileged mode can kernel code use to get direct access to the User mode registers R13 and R14?
In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?
When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?
Which one of the following features must any processor support to conform to the ARMv7-A architecture?
On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
An undefined instruction will cause an Undefined Instruction exception to be taken when:
Which of these processors is only available as a single core configuration?
A standard performance benchmark is being run on a single core ARM v7-A processor. The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?
TESTED 30 Nov 2025
